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US 9,070,545 B2Granted
Integrated circuit system including stacked chips for generating ID information
AssigneeSK hynix Inc.
InventorSang-Jin Byeon
Life of this patent
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Abstract
An integrated circuit system includes a first chip including a first node and configured to generate first identification information indicating the first chip in response to a voltage of the first node, a second chip including a second node and configured to generate second identification information indicating the second chip in response to a voltage of the second node, and a channel connected to the first node and the second node and generate a voltage difference between the first node and the second node.
Claims14
An integrated circuit system comprising:
- a channel connected to a first node and a second node and configured to generate a voltage difference between the first node and the second node;
- a first chip including the first node and a first replica channel obtained by modeling the channel and configured to generate first identification (ID) information corresponding to the first chip by comparing a voltage of the first node with one or more first comparison voltages generated from the first replica channel;
- and
- a second chip stacked on the first chip, and including the second node and a second replica channel obtained by modeling the channel and configured to generate second ID information corresponding to the second chip by comparing a voltage of the second node with one or more second comparison voltages generated from the second replica channel.
1 more element
An integrated circuit system comprising:
- a plurality of chips stacked on one another, each chip including an identification (ID) node;
- and
- a channel configured to connect the ID nodes to one another and generate a potential difference among the ID nodes,
- wherein each of the plurality of chips further includes a replica channel obtained by replicating the channel and generates corresponding ID information by comparing a voltage of the corresponding ID node with one or more comparison voltages generated from each corresponding replica channel.
1 more element
An integrated circuit system comprising:
- a first channel connected to a first node and a second node and configured to generate a voltage difference between the first node and the second node;
- a first chip including the first node and a first replica channel obtained by modeling the first channel and configured to generate first identification (ID) information corresponding to the first chip by comparing a voltage of the first node with one or more first comparison voltages generated from the first replica channel;
- a second chip stacked on the first chip, and including the second node and a second replica channel obtained by modeling the first channel and configured to generate second ID information corresponding to the second chip by comparing a voltage of the second node with one or more second comparison voltages generated from the second replica channel;
- and
- one or more second channels configured to apply comparison information to the first chip and the second chip,
- wherein the first chip and the second chip are configured to be activated when the first and second ID information correspond to the comparison information, respectively.
3 more elements
Dependencies are inferred from the claim text.