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US 9,065,449 B2Granted
High-speed divide-by-1.5 circuit with 50 percent duty cycle
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorAli Atesoglu
Life of this patent
Estimating the term…
Abstract
A divide-by-1.5 circuit includes a divide-by-3 circuit that and a frequency doubler circuit. The divide-by-3 circuit has few logic elements and provides glitch-free operation with a 50 percent duty cycle output. The frequency doubler circuit is based on phase-locked loop circuitry.
Claims20
A divide-by-1.5 circuit, comprising:
- a divide-by-3 circuit having an input coupleable to a source of an input signal;
- and
- a frequency doubler circuit comprising phase-locked loop (PLL) circuitry, the frequency doubler circuit having an input coupled to an output of the divide-by-3 circuit and having an output defining an output of the divide-by-1.5 circuit, the PLL circuitry having a comparison circuit, a loop filter, a voltage-controlled oscillator (VCO), and a loop divider circuit, the comparison circuit having a first input defining the input of the frequency doubler circuit, the loop divider circuit having an input coupled to an output of the VCO and an output coupled to a second input of the comparison circuit, an output of the VCO defining an output of the frequency doubler circuit, the loop filter connected to an output of the comparison circuit and an input of the VCO, the frequency doubler circuit coupled to a pre-divide-by-2 circuit having an output coupled to the first input of the comparison circuit, wherein the loop divider circuit comprises a loop divide-by-4 circuit including two loop divide-by-2 circuits in series with each other, and wherein each of the two loop divide-by-2 circuits consists of a D flip-flop.
A divide-by-1.5 circuit, comprising:
- a divide-by-3 circuit having an input coupleable to a source of an input signal, the divide-by-3 circuit comprising:
- a first D flip-flop having a non-inverted clock input coupled to a node defining the input of the divide-by-3 circuit;
- a second D flip-flop having a non-inverted clock input coupled to the node defining the input of the divide-by-3 circuit and having an input coupled to an output of the first D flip-flop;
- a third D flip-flop having an inverted clock input coupled to the node defining the input of the divide-by-3 circuit and having an input coupled to an output of the second D flip-flop;
- a first NOR gate having a first input coupled to the output of the first D flip-flop, a second input coupled to the output of the second D-flip-flop, and an output coupled to a D input of the first D flip-flop;
- and a second NOR gate having a first input coupled to an output of the third D flip-flop, a second input coupled to the output of the second D-flip-flop, and an output defining the output of the divide-by-3 circuit;
- and
- a frequency doubler circuit comprising phase-locked loop (PLL) circuitry, the frequency doubler circuit having an input coupled to an output of the divide-by-3 circuit and having an output defining an output of the divide-by-1.5 circuit, the PLL circuitry comprising a comparison circuit, a loop filter, a voltage-controlled oscillator (VCO), and a loop divider circuit, the comparison circuit having a first input defining the input of the frequency doubler circuit, the loop divider circuit having an input coupled to an output of the VCO and an output coupled to a second input of the comparison circuit, an output of the VCO defining an output of the frequency doubler circuit, the loop filter coupled to a node connected to an output of the comparison circuit and an input of the VCO, wherein the frequency doubler circuit comprises a pre-divide-by-2 circuit having an output coupled to the first input of the comparison circuit, the loop divider circuit including a loop divide-by-4 circuit having two loop divide-by-2 circuits in series with each other, and wherein each of the two loop divide-by-2 circuits consists of a D flip-flop.
5 more elements
Dependencies are inferred from the claim text.