Inductor-less 50% duty cycle wide-range divide-by-3 circuit

A local oscillator (LO) generation circuit for generating a local oscillating signal, comprising:

• a voltage-controlled oscillator (VCO) for outputting a global oscillating signal;
• a first frequency dividing circuit connected with the VCO and configured to produce an output signal having a first frequency one third that of the global oscillating signal and a duty cycle of 50%, wherein the first frequency dividing circuit comprises:
• first and second flip-flops;
• first, second, and third logic circuits, each configured to function equivalently to a logic OR gate, wherein an output of the first logic circuit is connected with an input of the first flip-flop, wherein an output of the second logic circuit is connected with an input of the second flip-flop, wherein an output of the first flip-flop is connected with a first input of the first logic circuit and with a first input of the second logic circuit, wherein an output of the second flip-flop is connected with a second input of the first logic circuit and with a second input of the second logic circuit, wherein the output of the first flip-flop is connected with a first input of the third logic circuit, and wherein the output of the second flip-flop is connected with a second input of the third logic circuit;
• and
• a second frequency dividing circuit configured to generate an output waveform having a second frequency that is one half that of an input waveform, wherein the input waveform is based on an output of the third logic circuit;
• and
• a third frequency dividing circuit configured to generate the local oscillating signal based on the output signal from the first frequency dividing circuit.

An apparatus for wireless communications, comprising:

• at least one antenna;
• and
• a transmitter configured to transmit, via the at least one antenna, a data signal mixed with a local oscillating signal, wherein the local oscillating signal is generated by a local oscillator (LO) generation circuit, comprising:
• a voltage-controlled oscillator (VCO) for outputting a global oscillating signal;
• a first frequency dividing circuit connected with the VCO and configured to produce an output signal having a first frequency one third that of the global oscillating signal and a duty cycle of 50%, wherein the first frequency dividing circuit comprises:
• first and second flip-flops;
• first, second, and third logic circuits, each configured to function equivalently to a logic OR gate, wherein an output of the first logic circuit is connected with an input of the first flip-flop, wherein an output of the second logic circuit is connected with an input of the second flip-flop, wherein an output of the first flip-flop is connected with a first input of the first logic circuit and with a first input of the second logic circuit, wherein an output of the second flip-flop is connected with a second input of the first logic circuit and with a second input of the second logic circuit, wherein the output of the first flip-flop is connected with a first input of the third logic circuit, and wherein the output of the second flip-flop is connected with a second input of the third logic circuit;
• and
• a second frequency dividing circuit configured to generate an output waveform having a second frequency that is one half that of an input waveform, wherein the input waveform is based on an output of the third logic circuit;
• and
• a third frequency dividing circuit configured to generate the local oscillating signal based on the output signal from the first frequency dividing circuit.