Terminations and couplings between chips and substrates
AssigneeZhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co. Ltd.
InventorsDror Hurwitz, Alex Huang
Life of this patent
Estimating the term…
Abstract
A method of attaching a chip to the substrate with an outer layer consisting of via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method consisting of optionally removing an organic varnish, positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and applying heat to melt the solder bumps and to wet the ends of the vias with solder.
Claims29
A multilayer composite electronic structure comprising at least one pair of feature layers extending in an X-Y plane, each adjacent pair of feature layers being separated by an inner via layer, the via layer comprising via posts that couple adjacent feature layers in a Z direction perpendicular to the X-Y plane, the via posts being embedded in an inner layer dielectric, the multilayer composite electronic structure further comprising termination pads consisting of an outer layer of via pillars embedded in an outer dielectric material, thinned to expose ends of the outer layer of via pillars.
Dependencies are inferred from the claim text.