Counter, counting method, ad converter, solid-state imaging device, and electronic device
AssigneeSony Corporation
InventorYasuaki Hisamatsu
Life of this patent
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Abstract
A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.
Claims9
A counter configured to perform counting at both edges of an input clock to output an addition value or a subtraction value for a previous count value and a next count value, comprising:
- a first latch circuit that latches a state of the input clock;
- a second latch circuit that latches an output from the first latch circuit;
- a flip-flop circuit that holds data of a 0th bit of the previous count value;
- and
- a first circuit that performs count correction on the data of the 0th bit and subsequent bits of the previous count value and the next count value on the basis of an output of the second latch circuit and the 0th bit of the previous count value which is an output of the flip-flop circuit.
A counting method performing counting at both edges of an input clock to output an addition value or a subtraction value for a previous count value and a next count value, the method comprising:
- latching a state of the input clock by a first latch circuit;
- latching an output of the first latch circuit by a second latch circuit;
- holding data of a 0th bit of the previous count value by a flip-flop circuit;
- and
- performing count correction on the data of the 0th bit and subsequent bits of the previous count value and the next count value based on the basis of an output of the second latch circuit and the 0th bit of the previous count value which is an output of the flip-flop circuit.
An AD converter comprising:
- a comparator circuit configured to compare a signal level to a threshold value;
- and
- a counter configured to perform, in a period until an output of the comparator circuit is inverted, counting at both edges of an input clock to output an addition value or a subtraction value for a previous count value and a next count value,
- wherein the counter includes
- a first latch circuit configured to latch a state of the input clock;
- a second latch circuit configured to latch an output from the first latch circuit;
- a flip-flop circuit configured to hold data of a 0th bit of the previous count value;
- and
- a first circuit configured to perform count correction on the data of the 0th bit and subsequent bits of the previous count value and the next count value on the basis of an output of the second latch circuit and the 0th bit of the previous count value which is an output of the flip-flop circuit.
A solid-state imaging device comprising:
- a pixel array circuit configured to output a pixel signal corresponding to incident light;
- and
- an AD converter configured to AD convert the pixel signal output from the pixel array circuit,
- wherein the AD converter includes
- a comparator circuit configured to compare a level of the pixel signal output by the pixel array circuit to a threshold value, and
- a counter configured to perform, in a period until an output of the comparator circuit is inverted, counting at both edges of an input clock to output an addition value or a subtraction value for a previous count value and a next count value, and
- the counter includes
- a first latch circuit configured to latch a state of the input clock;
- a second latch circuit configured to latch an output from the first latch circuit;
- a flip-flop circuit configured to hold data of a 0th bit of the previous count value;
- and
- a first circuit configured to perform count correction on the data of the 0th bit and subsequent bits of the previous count value and the next count value on the basis of an output of the second latch circuit and the 0th bit of the previous count value which is an output of the flip-flop circuit.
An electronic device comprising:
- an imaging circuit using a solid-state imaging device, wherein the solid-state imaging device includes
- a pixel array circuit configured to output a pixel signal corresponding to incident light, and
- an AD converter configured to AD convert the pixel signal output from the pixel array circuit,
- the AD converter includes
- a comparator circuit configured to compare a level of the pixel signal output from the pixel array circuit to a threshold value, and
- a counter configured to perform, in a period until an output of the comparator circuit is inverted, counting at both edges of an input clock to output an addition value or a subtraction value for a previous count value and a next count value,
- the counter includes
- a first latch circuit configured to latch a state of the input clock;
- a second latch circuit configured to latch an output from the first latch circuit;
- a flip-flop circuit configured to hold data of a 0th bit of the previous count value;
- and
- a first circuit configured to perform count correction on the data of the 0th bit and subsequent bits of the previous count value and the next count value on the basis of an output of the second latch circuit and the 0th bit of the previous count value which is an output of the flip-flop circuit.
Dependencies are inferred from the claim text.