Distributed metal routing

A semiconductor device comprising:

• a first conductive layer on a substrate having a first plurality of conductive lines and a second plurality of conductive lines, wherein the first plurality of conductive lines parallel to and interleaved with the second plurality of conductive lines, at least some of the first plurality of conductive lines serving as gates for transistors formed in the substrate;
• a second conductive layer over the first conductive layer and separated therefrom by a dielectric layer, the second conductive layer comprising a third plurality of conductive lines and a fourth plurality of conductive lines parallel to and interleaved with the third plurality of conductive lines, the third and four pluralities of conductive lines being perpendicular to the first and second pluralities of conductive lines, a first plurality of the fourth plurality of conductive lines connected to a first source, a second plurality of the fourth plurality of conductive lines connected to a second source different from the first source;
• and
• a plurality of interlayer interconnections, each of the plurality of interlayer interconnections extending through the dielectric layer from one of the first or second pluralities of conductive lines to one of the third or fourth plurality of conductive lines.

A semiconductor device comprising:

• a first conductive layer on a substrate, the first conductive layer having a first plurality of conductive lines and a second plurality of conductive lines, parallel to and interleaved with the first plurality of conductive lines, at least some of the first plurality of conductive lines serving as gates for transistors formed in the substrate and wherein at least some of the plurality of second conductive lines in contact with the substrate;
• and
• a second conductive layer over the first conductive layer and separated therefrom by a dielectric layer, the second conductive layer comprising a third plurality of conductive lines and a fourth plurality of conductive lines parallel to and interleaved with the third plurality of conductive lines, the third and four pluralities of conductive lines being perpendicular to the first and second pluralities of conductive lines, wherein the fourth plurality of conductive lines provides connection to signals to be distributed to multiple points on the semiconductor device;
• and
• a plurality of interlayer interconnections, each of the plurality of interlayer interconnections extending through the dielectric layer from one of the first or second pluralities of conductive lines to one of the third or fourth plurality of conductive lines.