US 9,040,987 B2Granted

Semiconductor device

AssigneeE Ink Holdings Inc.

InventorsWei-Chou Lan, Ted-Hong Shinn, Henry Wang, Chia-Chun Yeh

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Abstract

A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose the fourth cavity.

Claims13

Dependent claims

A semiconductor device, disposed on a base-plate, the semiconductor device comprising:

a substrate, having a surface and a first cavity located at the surface;
a metal layer, disposed on the substrate, covering the surface and covering an inner-wall of the first cavity so as to define a second cavity corresponding to the first cavity;
an insulating layer, disposed on the metal layer and covering the metal layer and an inner-wall of the second cavity so as to define a third cavity corresponding to the second cavity;
a semiconductor layer, disposed on the insulating layer, exposing a portion of the insulating layer and covering an inner-wall of the third cavity so as to define a fourth cavity corresponding to the third cavity;
a drain, disposed on the semiconductor layer and covering a portion of the semiconductor layer and a portion of the insulating layer, wherein the drain exposes the fourth cavity;
and
a source, disposed on the semiconductor layer and covering a portion of the semiconductor layer and a portion of the insulating layer, wherein the source exposes the fourth cavity.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/721,026Filed 20 Dec 2012
Priority: TW 101106741 A1 Mar 2012
Published: US 2013/0228779 A15 Sep 2013
Granted: 26 May 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/67
Insulated-gate field-effect transistors [IGFET]: thin-film transistors [TFT]
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
H10D 30/6758
Thin-film transistors [TFT]: characterised by the insulating substrates
H10D 86/411
Characterised by multiple TFTs: characterised by materials, geometry or structure of the substrates

Family

US 2013/0228779 A1Pre-grant publication · published 5 Sep 2013
US 9,040,987 B2This patent

From the US filing history. Foreign family members aren’t listed.

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