Three dimensional integrated circuit having a resistance measurement structure and method of use

A three-dimensional integrated circuit (3DIC) comprising:

• a top chip, wherein the top chip includes at least one active device;
• an interposer, wherein the interposer includes conductive routing layers and vias;
• a second chip electrically connected to the top chip, wherein the second chip includes at least one active device;
• a first plurality of conductive connectors, wherein the first plurality of conductive connectors electrically connected to the top chip;
• a second plurality of conductive connectors, wherein the second plurality of conductive connectors are electrically connected to the second chip;
• at least one conductive line over at least one of the top chip, the second chip or the interposer, wherein the at least one conductive line traces a perimeter of the at least one of the top chip, the second chip or the interposer substantially parallel to an outer edge of the at least one of the top chip, the second chip or the interposer, and the at least one conductive line is configured to electrically connect the first plurality of conductive connectors or the second plurality of conductive connectors;
• and
• at least one testing element over at least one of the top chip, the second chip or the interposer, wherein each of the at least one testing element is electrically connected to the first plurality of conductive connectors or the second plurality of conductive connectors.

A three-dimensional integrated circuit (3DIC) comprising:

• a chip, wherein the chip includes at least one active device;
• an interposer electrically connected to the chip;
• at least one conductive line on at least one of the chip or the interposer, wherein the at least one conductive line traces a perimeter of the at least one of the top chip or the interposer;
• and
• at least one testing element over at least one of the chip or the interposer, wherein each of the at least one testing element is usable to determine an integrity of the at least one conductive line.