US 9,040,843 B2Granted

Multilayer printed wiring board

AssigneeIbiden Co., Ltd.

InventorsYukihiko Toyoda, Yoichiro Kawamura, Tomoyuki Ikeda

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Abstract

A multilayered printed circuit board including a substrate, a multilayered structure formed on the substrate and including multiple conductor circuits and multiple interlaminar resin insulating layers, and a stack-via structure having multiple via-holes and formed in the multilayered structure such that the via-holes are piled through the interlaminar resin insulating layers in the multilayered structure. The interlaminar resin insulating layers include an outermost interlaminar resin insulating layer forming an outermost layer of the interlaminar resin insulating layers and having a coefficient of linear expansion which is equal to or smaller than coefficients of linear expansion of the interlaminar resin insulating layers other than the outermost interlaminar resin insulating layer.

Claims22

Dependent claims

A multilayered printed circuit board, comprising:

a substrate;
a multilayered structure formed on the substrate and comprising a plurality of conductor circuits and a plurality of interlaminar resin insulating layers;
and
a stack-via structure comprising a plurality of via-holes and formed in the multilayered structure such that the via-holes are piled through the interlaminar resin insulating layers in the multilayered structure,
wherein each of the via-holes has a filled via structure portion comprising a metal portion such that the metal portion is filling an opening of a respective one of the interlaminar resin insulating layers, the plurality of via-holes of the stack-via structure includes an outermost via-hole of the stack-via structure, and the outermost via-hole of the stack-via structure has a recess portion on an outer surface of the outermost via-hole.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/617,012Filed 14 Sep 2012 · continuation
Priority: JP 2001-07306614 Mar 2001
Published: US 2013/0008701 A110 Jan 2013
Granted: 26 May 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H05K 1/115
Printed elements for providing electric connections to or between printed circuits: via connections; Lands around holes or via connections
H05K 1/0271
Details: arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal…
H05K 1/113
Directly combined with via connections: via provided in pad; Pad over filled via
H05K 1/116
Via connections; Lands around holes or via connections: lands, clearance holes or other lay-out details concerning the surrounding of a via

Family

PCT/JP02/02336Parent of this continuation · filed 13 Mar 2002
Application12/099,957Parent of this continuation · filed 9 Apr 2008
Application13/004,325Parent of this continuation · filed 11 Jan 2011
US 2013/0008701 A1Pre-grant publication · published 10 Jan 2013
US 8,324,512 B2Parent of this continuation
US 8,030,579 B2Parent of this continuation
Application10/257,370Parent of this continuation
US 7,371,974 B2Parent of this continuation
US 2003/0178229 A1Published application
US 2008/0190658 A1Published application
US 2011/0108311 A1Published application
US 9,040,843 B2This patent

From the US filing history. Foreign family members aren’t listed.

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