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US 9,040,416 B2Granted
Manufacturing method of metal wire and thin transistor array panel
AssigneeSamsung Display Co., Ltd.
InventorDong-Jin Son
Life of this patent
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Abstract
A manufacturing method of a wire including: forming a lower layer on a substrate; forming a middle layer on the lower layer; forming an upper layer on the middle layer; forming, exposing, and developing a photoresist layer on the upper layer to form a photoresist pattern; and etching the upper layer, the middle layer, and the lower layer by using the photoresist pattern as a mask to form a wire such that the upper layer covers an end of the middle layer.
Claims4
A method of manufacturing a thin film transistor array panel, comprising:
- forming a first lower layer on a substrate;
- forming a first middle layer on the first lower layer;
- forming a first upper layer on the first middle layer;
- forming a photoresist pattern on the first upper layer using a first developing process;
- forming a first signal line by etching the first upper layer, the first middle layer, and the first lower layer by using the photoresist pattern as a mask;
- forming a thin film transistor connected to the first signal line;
- forming a second signal line connected to the thin film transistor;
- and
- forming a first electrode connected to the second signal line,
- wherein:
- the first upper layer covers an end of the first middle layer;
- the first lower layer, the first middle layer, and the first upper layer are formed in a sputtering device including a mask aligned with edges of the substrate;
- the mask is aligned to overlap the substrate by a first width when forming the first middle layer;
- the mask is aligned to overlap the substrate by a second width when forming the first upper layer;
- and
- the first width is less than the second width.
13 more elements
A method of manufacturing a thin film transistor array panel, comprising:
- forming a first lower layer on a substrate;
- forming a first middle layer on the first lower layer;
- forming a first upper layer on the first middle layer;
- forming a photoresist pattern on the first upper layer using a first developing process;
- forming a first signal line by etching the first upper layer, the first middle layer, and the first lower layer by using the photoresist pattern as a mask;
- forming a thin film transistor connected to the first signal line;
- forming a second signal line connected to the thin film transistor;
- and
- forming a first electrode connected to the second signal line,
- wherein:
- the first upper layer covers an end of the first middle layer;
- the forming of the second signal line further comprises:
- forming a second lower layer on the substrate;
- forming a second middle layer on the second lower layer;
- forming a second upper layer on the second middle layer;
- forming a second photoresist pattern on the second upper layer using a second developing process;
- and
- etching the second upper layer, the second middle layer, and the second lower layer by using the photoresist pattern as a mask;
- the second upper layer covers the end of the second middle layer;
- the second lower layer, the second middle layer, and the second upper layer are formed in a sputtering device comprising a mask aligned with edges of the substrate;
- the mask is aligned to overlap the substrate by a third width when forming the second middle layer;
- the mask is aligned to overlap the substrate by a fourth width when forming the second upper layer;
- and
- the third width is less than the fourth width.
21 more elements
Dependencies are inferred from the claim text.