Techniques for wafer-level processing of QFN packages

A wafer-level package device comprising:

• an integrated circuit die having a surface;
• an encapsulation structure disposed over the surface;
• at least one pillar extending from the surface through the encapsulation structure, the at least one pillar having an end distal from the surface including a portion that extends beyond the encapsulation structure, the at least one pillar configured to provide an electrical interconnection to the integrated circuit die;
• and
• a solder layer disposed over the end of the at least one pillar, the solder layer extending from the encapsulation structure over a vertical sidewall of the portion of the at least one pillar that extends beyond the encapsulation structure.

A process comprising:

• forming at least one pillar over a semiconductor wafer;
• forming an encapsulation structure over the semiconductor wafer, the encapsulation structure at least substantially encapsulating the at least one pillar;
• applying under bump metallization (UBM) over the at least one pillar;
• and
• applying a solder layer to the under bump metallization (UBM), the solder layer extending from the encapsulation structure over a vertical sidewall of the under bump metallization (UBM).

A wafer-level package device comprising:

• an integrated circuit die having a surface;
• at least one pillar extending from the surface, the at least one pillar having an end distal from the surface, the at least one pillar configured to provide an electrical interconnection to the integrated circuit die;
• an encapsulation structure disposed over the surface, the encapsulation structure at least partially enclosing the at least one pillar;
• under bump metallization (UBM) disposed over the at least one pillar and encapsulation structure;
• and
• a solder layer disposed over the end of the at least one pillar, the solder layer extending from the encapsulation structure over a vertical sidewall of the under bump metallization (UBM).