Semiconductor chip with power gating through silicon vias

A method of power gating a semiconductor chip, the method comprising:

• providing a semiconductor chip, the semiconductor chip including:
• a semiconductor substrate having a frontside surface and a backside surface, the backside surface being coupled to a ground,
• a functional circuit in the semiconductor substrate at the frontside surface, the functional circuit electrically isolated from the semiconductor substrate,
• a through silicon via (TSV) having a front-end surface, a back-end surface, and a lateral surface, the back-end surface and lateral surface of the TSV being in the semiconductor substrate, and the front-end surface of the TSV being substantially parallel to the frontside surface of the semiconductor substrate,
• an antifuse material deposited between the back-end and lateral surfaces of the TSV and the semiconductor substrate, the antifuse material being configured to insulate the TSV from the semiconductor substrate, and
• a functional ground layer insulated from the semiconductor substrate and electrically coupled with the TSV, and the functional circuit, wherein the functional ground layer is configured to conduct a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby electrically connecting the functional circuit to the ground;
• determining whether the functional circuit is functional;
• and
• if the functional circuit is functional, blowing the antifuse material with a program voltage to ground the functional circuit to the substrate ground.