Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof

A method for fabricating a stacked microelectronic package, comprising:

• obtaining a partially-completed stacked microelectronic package having at least upper and lower package layers, the upper and lower package layers each comprising:
• a package body;
• a microelectronic device embedded in the package body;
• and
• one or more dielectric layers overlying the package body and the microelectronic device;
• and
• a plurality of package edge conductors formed in the one or more dielectric layers and extending from the microelectronic device to a sidewall of the stacked microelectronic package, the plurality of package edge conductors exposed through the sidewall of the stacked microelectronic package;
• producing an unpatterned metal-containing epoxy layer contacting the plurality of package edge conductors by dispensing a metal-containing epoxy over the sidewall of the package body, curing the metal-containing epoxy, and cutting through the metal-containing epoxy during package singulation;
• and
• patterning the unpatterned metal-containing epoxy layer by removing selected portions of the electrically-conductive layer at one or more surfaces created when cutting through the metal-containing epoxy layer during package singulation, the unpatterned metal-containing epoxy layer patterned to produce a plurality of sidewall conductors interconnecting the microelectronic devices included within the upper and lower package layers.