Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods

A method of forming an integrated circuit device, the method comprising:

• forming a plurality of insulating patterns alternating with a plurality of semiconductor patterns on a substrate;
• performing a first etching process to etch the plurality of insulating patterns and the plurality of semiconductor patterns to form a preliminary hole exposing sidewalls of the plurality of insulating patterns and the plurality of semiconductor patterns, wherein an upper one of the plurality of semiconductor patterns relative to the substrate is laterally etched more than a lower one of the plurality of semiconductor patterns relative to the substrate;
• and then
• performing a second etching process to laterally etch the sidewalls of the plurality of semiconductor patterns to expand the preliminary hole into a hole, wherein the upper one of the plurality of semiconductor patterns is laterally etched less than the lower one of the plurality of semiconductor patterns.

A method of forming a vertical nonvolatile memory device, the method comprising:

• forming a plurality of insulating patterns alternating with a plurality of semiconductor patterns on a substrate, wherein the plurality of semiconductor patterns have impurity concentrations that are different from each other;
• etching the plurality of insulating patterns and the plurality of semiconductor patterns to form a preliminary hole, the preliminary hole having a sidewall that is slanted with respect to an upper surface of the substrate;
• and
• laterally etching the plurality of semiconductor patterns exposed by the preliminary hole to form a hole, wherein sidewalls of the plurality of semiconductor patterns comprising a sidewall of the hole are aligned along a plane substantially perpendicular to the upper surface of the substrate.