Low loss SiC MOSFET

A process for fabrication of a silicon carbide (SiC) vertical power MOSFET structure, the process comprising:

• providing a SiC substrate including an upper layer of a first dopant type defining a drift region extending from an upper surface of the substrate depthwise into the substrate;
• implanting a pair of body regions in the upper layer and adjoining the upper surface of the substrate, the body regions being spaced apart about the drift region and of a second dopant type opposite the first dopant type, each of the body regions having opposite lateral peripheries each forming a first PN junction with the drift region;
• implanting a pair of source regions spaced apart in each body region across the upper surface of the substrate to define a source contact region and positioned with respect to the lateral peripheries of the body region to form a second PN junction spaced laterally from the first PN junction and to define a channel region along the upper surface between the first and second PN junctions;
• forming a gate oxide layer of a first thickness on the upper surface extending over each channel region;
• forming a gate conductor contacting the gate oxide layer;
• forming a source conductor contacting the source regions and the body region therebetween;
• and
• forming a terraced dielectric layer on the upper surface extending between each of the gate oxide layers over the drift region, the terraced dielectric layer having a second thickness greater than the first thickness of the gate oxide layer;
• wherein the terraced dielectric layer includes opposite tapered edges which intercept the body regions at the upper surface of the substrate adjacent the first PN junctions and which overlap portions of the body regions within the substrate below the upper surface.