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US 9,040,367 B2Granted
Latch-up immunity nLDMOS
AssigneeGlobalfoundries Singapore Pte. Ltd.
InventorDa-Wei Lai
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Abstract
An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.
Claims8
A method comprising:
- providing in a substrate a dual voltage n-well (DVNW) region;
- providing a high voltage p-well (HVPW) region in the DVNW region;
- providing bulk and source regions in the HVPW region;
- providing a drain region in the DVNW region, separate from the HVPW region;
- providing a polysilicon gate over a portion of the HVPW region and the DVNW region;
- and
- providing in the source region in the HVPW region, second and third N+ regions and a first P+ region, the second and third N+ regions being separated by the first P+ region.
4 more elements
Dependencies are inferred from the claim text.