Method and sequential monitoring overlay system for track circuits

A sequential monitoring system for an interlocking logic system and a track circuit system including a plurality of track circuits, each of said track circuits having a state, said sequential monitoring system comprising:

• an interface between said interlocking logic system and said track circuit system;
• and
• a processor structured to monitor the state of each of said track circuits, validate a sequence of state changes of said track circuits, and interrupt and correct invalid track circuit state indications between said track circuit system and said interlocking logic system,
• wherein said interface normally passes inputs from said track circuit system to outputs to said interlocking logic system, and
• wherein when an out of sequence event is detected by said processor, said processor applies a quarantine to a minimum of three of said track circuits in a quarantined area, wherein said out of sequence event is caused by one of said three of said track circuits changing state from occupied to unoccupied without an adjacent one of said three of said track circuits having an occupied state, wherein said quarantine forces a state of said one said three of said track circuits as received by said interlocking logic system to be occupied, thereby inhibiting use of an unoccupied track circuit in the quarantined area.

A sequential monitoring overlay system for an interlocking logic system and a track circuit system including a plurality of track circuits, each of said track circuits having a state, said sequential monitoring overlay system comprising:

• an overlay interface between said interlocking logic system and said track circuit system;
• and
• a processor structured to monitor the state of each of said track circuits, validate a sequence of state changes of said track circuits, and interrupt and correct invalid track circuit state indications between said track circuit system and said interlocking logic system,
• wherein said interface normally passes inputs from said track circuit system to outputs to said interlocking logic system, and
• wherein when an out of sequence event is detected by said processor, said processor applies a quarantine to a minimum of three of said track circuits in a quarantined area, wherein said out of sequence event is caused by one of said three of said track circuits changing state from occupied to unoccupied without an adjacent one of said three of said track circuits having an occupied state, wherein said quarantine forces a state of said one said three of said track circuits as received by said interlocking logic system to be occupied, thereby inhibiting use of an unoccupied track circuit in the quarantined area.