Register circuits and methods of storing data in a register circuit
AssigneeXilinx, Inc.
InventorBrian C. Gaide
Life of this patent
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Abstract
A register circuit adapted to store data is described. The register circuit comprises a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input; and a delay element coupled to the master-slave flip flop, the delay element receiving a reference clock signal and generating a slave clock signal the slave clock signal which is delayed relative to a master clock signal. A method of storing data in a register circuit is also described.
Claims20
A register circuit adapted to store data, the register circuit comprising:
- a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input;
- and
- a control circuit coupled to the master-slave flip flop, the control circuit receiving a reference clock signal and generating the slave clock signal which is delayed relative to a master clock signal;
- wherein the control circuit comprises a first delay element establishing a pulse width of the slave clock signal, and a second delay element establishing a delay of the slave clock signal relative to the master clock signal.
A register circuit adapted to store data, the register circuit comprising:
- a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input, a master clock signal and a slave clock signal;
- a slave pulse generator coupled to the master-slave flip flop, the slave pulse generator receiving a reference clock signal and generating the slave clock signal which is delayed relative to the master clock signal;
- and
- a slave pulse detector coupled to receive the master clock signal and the slave clock signal, the slave pulse detector controlling the generation of the master clock signal.
A method of storing data in a register circuit, the method comprising:
- coupling data to a master-slave flip flop;
- coupling a reference clock signal to a control circuit;
- generating a slave clock signal using a first delay element to establish a pulse width of the slave clock signal;
- establishing a delay of the slave clock signal relative to a master clock signal using a second delay element;
- and
- coupling the master clock signal and the slave clock signal to the master-slave flip flop.
Dependencies are inferred from the claim text.