Jitter suppression in type I delay-locked loops

A system for generating a jitter-suppressed digital clock signal comprising:

• an input component for generating a jitter-suppressed periodic digital output signal, the input component including:
• a delay-locked loop (DLL) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal further including
• a delay line of a first controllable phase delay, responsive to the periodic digital input signal for generating a delayed version thereof as the periodic digital output signal;
• a phase detector responsive to the periodic digital input and output signals for generating a phase error signal representative of a difference in phase between the periodic digital input and output signals;
• a loop filter responsive to the phase error signal for generating a control voltage, the control voltage applied as a control input to the delay line for adjusting the length of the first controllable phase delay to match the phase of the periodic digital output signal with the phase of the periodic digital input signal;
• and
• a deskew element responsive to the DLL periodic digital input signal and the DLL periodic digital output signal for suppressing a jitter component present in the DLL periodic digital output signal by synchronizing transitions in the DLL periodic digital output signal with transitions in the DLL periodic digital input signal and generating a final jitter-suppressed output signal;
• and
• an output component for generating a digital clock signal from the jitter-suppressed output signal, the output component including:
• a secondary delay line of a second controllable phase delay, responsive to the jitter-suppressed output signal for introducing the second controllable phase delay to create the digital clock signal at the output thereof;
• and
• a secondary filter element responsive to the control voltage for creating a secondary control voltage input for the secondary delay line to phase match the jitter-suppressed output signal with the created digital clock signal.

A method of suppressing jitter in a periodic digital output signal from a delay-locked loop (DLL), the method comprising:

• receiving a periodic digital input signal having a predetermined period;
• delaying the input periodic digital signal by a period of time to form the periodic digital output signal;
• comparing a phase of the periodic digital input signal to a phase of the periodic digital output signal and forming a phase error output signal representative of a phase difference therebetween;
• generating a loop control signal from the phase error output signal for adjusting the period of time to reduce the value of the phase error signal;
• and
• deskewing the periodic digital output signal with respect to the periodic digital input signal to suppress a jitter component present in the periodic digital output signal and create a final output signal, deskewing the periodic digital output signal comprises latching a transition of the periodic digital output signal with the periodic digital input signal such that the final output signal is created only when the periodic digital input signal and the periodic digital output signal are of a same state.