Interconnection structure

A semiconductor device comprising an interconnection structure which comprises:

• first and second differential signal interconnections provided to transmit a differential signal;
• and
• first and second voltage interconnections applied with predetermined voltages,
• wherein said first voltage interconnection, said first differential signal interconnection, said second differential signal interconnection and said second voltage interconnection are lead pins and arranged in this order,
• wherein an interval between said first and second differential signal interconnections in a first direction is longer than an interval between said first voltage interconnection and said first differential signal interconnection in the first direction and is longer than an interval between said second differential signal interconnection and said second voltage interconnection in the first direction,
• wherein when a first connection point and a second connection point nearest to said first connection point are provided on any of said first and second differential signal interconnections and said first and second voltage interconnections, a distance between said first connection point and said second connection point is in a range of 1/16 of a wavelength of the differential signal to ⅛ of the wavelength thereof, and
• wherein said first differential signal interconnection and said second differential signal interconnection are arranged without another interconnection between them.

A semiconductor device comprising:

• a mounting plate having a principal surface and a rear surface opposite to the principal surface;
• a semiconductor chip having a first main surface and a second main surface opposite to the first main surface, the semiconductor chip mounted on the principal surface of the mounting plate such that the second main surface of the semiconductor chip being faced to the principal surface of the mounting plate, a plurality of electrodes formed on the first main surface;
• and
• a plurality of leads arranged along the semiconductor chip, each of the leads being electrically connected with each of the electrodes via a plurality of wires respectively, the leads including a first lead for first power supply, a second lead for first differential signal, a third lead for second differential signal and a fourth lead for second power supply,
• wherein the first lead, second lead, third lead and fourth lead are arranged in this order,
• wherein a first length between the second lead and the third lead in a first direction is greater than a second length between the first lead and the second lead in the first direction, and
• wherein the first lead and the second lead are arranged without another lead between them.