US 9,006,890 B2Granted

Solder in cavity interconnection structures

AssigneeIntel Corporation

InventorsChuan Hu, Shawna M Liff, Gregory S Clemons

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Abstract

The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Claims7

Dependent claims

A microelectronic device, comprising:

a first substrate having a plurality of bond pads proximate a contact surface of the first substrate;
a first dielectric layer disposed over the plurality of first substrate bond pads and the first substrate contact surface, wherein the first dielectric layer has a plurality of cavities extending therethrough to each of the plurality of first substrate bond pads, wherein inter-cavity walls of the first dielectric layer reside between adjacent cavities, and wherein the inter-cavity walls have sloped sidewalls, wherein the inter-cavity walls include contact structures formed between each of the adjacent cavities, and wherein the inter-cavity wall contact structures are substantially planar to the first substrate contact surface;
a second substrate having a plurality of contact lands proximate a contact surface of the second substrate;
and
solder interconnections between the plurality of first substrate bond pads and corresponding plurality of the second substrate contact lands.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/740,698Filed 14 Jan 2013 · division
Priority: 23 Mar 2011
Published: US 2013/0128484 A123 May 2013
Granted: 14 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification29 codes

H10W 72/20
Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
H05K 1/181
Structurally associated with non-printed electric components: associated with surface mounted components
H10W 74/012
Manufacture or treatment: of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
H10W 74/114
The semiconductor body being completely enclosed: by a substrate and the encapsulations

Family

Application13/069,601Parent of this division · filed 23 Mar 2011
US 2013/0128484 A1Pre-grant publication · published 23 May 2013
US 2012/0241965 A1Published application
US 8,936,967 B2Related patent
US 9,006,890 B2This patent

From the US filing history. Foreign family members aren’t listed.

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