Semiconductor device and method of forming stress relief layer between die and interconnect structure

A semiconductor device, comprising:

• a semiconductor die;
• a conductive pillar formed around the semiconductor die;
• a stress relief insulating layer formed over the semiconductor die and the conductive pillar, the stress relief insulating layer including a first thickness over the semiconductor die and a second thickness less than the first thickness over the conductive pillar;
• an encapsulant deposited over the semiconductor die and around the conductive pillar;
• and
• a first interconnect structure formed over the stress relief insulating layer.

A semiconductor device, comprising:

• a semiconductor die;
• a conductive pillar formed around the semiconductor die;
• a stress relief insulating layer formed over the semiconductor die and the conductive pillar including an opening in the stress relief insulating layer over the semiconductor die;
• and
• a first interconnect structure formed over the stress relief insulating layer.

A semiconductor device, comprising:

• a semiconductor die;
• a conductive pillar formed around the semiconductor die;
• and
• a stress relief insulating layer formed over the semiconductor die and the conductive pillar including an opening in the stress relief insulating layer over the semiconductor die.