Source/drain extension control for advanced transistors
AssigneeSuVolta, Inc.
InventorsPushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
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Abstract
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
Claims20
A semiconductor die, comprising:
- a plurality of transistors, the plurality of transistors each having:
- a gate with an effective gate length;
- a source region;
- a drain region;
- an epitaxially grown channel layer below the gate and extending between the source region and the drain region;
- a first highly doped layer below the channel layer and coextensive therewith, the first highly doped layer effective to set a depletion depth for said plurality of transistors;
- and
- wherein some of the plurality of transistors have a second highly doped layer below the channel layer and above the first highly doped layer;
- wherein some of the plurality of transistors include a source and drain extension region;
- and
- wherein some of the plurality of transistors are haloless.
A semiconductor structure on a bulk silicon substrate, the structure comprising:
- a transistor having a gate, a source region and a drain region;
- an undoped epitaxially grown channel layer below the gate and extending between the source region and the drain region;
- a first highly doped layer below the channel layer, the highly doped layer extending laterally across the channel layer;
- a second highly doped layer below the first highly doped layer and coextensive therewith, the second highly doped layer being doped to a concentration sufficient to set the depletion width for the transistor;
- a third highly doped layer below the second highly doped layer and coextensive therewith, the third highly doped layer being doped to a concentration sufficient to serve as a punch through suppression layer;
- and
- wherein the transistor is haloless.
Dependencies are inferred from the claim text.