High sheet resistor in CMOS flow

An integrated circuit, comprising:

• a substrate;
• an n-channel metal oxide semiconductor (NMOS) transistor located in and on said substrate, said NMOS transistor including:
• an NMOS gate located on an NMOS gate dielectric layer on said substrate, said NMOS gate including polysilicon;
• sidewall spacers abutting said NMOS gate, said sidewall spacers including dielectric material;
• n-type n-channel source/drain (NSD) layers in said substrate adjacent to said NMOS gate, said NSD layers containing n-type dopants;
• a p-channel metal oxide semiconductor (PMOS) transistor located in and on said substrate, said PMOS transistor including:
• a PMOS gate located on a PMOS gate dielectric layer on said substrate, said PMOS gate including polysilicon;
• sidewall spacers abutting said PMOS gate, said sidewall spacers including dielectric material;
• p-type p-channel source/drain (PSD) layers in said substrate adjacent to said PMOS gate, said PSD layers containing p-type dopants;
• a counterdoped polysilicon gate material resistor located over said substrate;
• said counterdoped polysilicon gate material resistor including:
• a resistor layer, said resistor layer including polysilicon, said resistor layer having a body region containing n-type dopants as located in said NSD layers and p-type dopants as located in said PSD layers, and said resistor layer having head regions at each end of said body region, said head regions having a same conductivity type as said body region;
• a resistor silicide block layer located over said body region, said resistor silicide block layer including different dielectric material than said sidewall spacers;
• and
• silicide layers on said head regions, said NSD layers and said PSD layers;
• and
• a pre-metal dielectric (PMD) layer located over said silicide layers and said resistor silicide block layer.