Method and structure for controlling stress in a transistor channel
AssigneeInternational Business Machines Corporation
InventorsHaining S. Yang, Huilong Zhu
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Abstract
A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of the n-type device and the p-type device such that a thickness of the shallow-trench-isolation oxide adjacent to the n-type device is different from a thickness of the shallow-trench-isolation oxide adjacent to the p-type device, and forming a strain layer over the semiconductor substrate.
Claims17
A semiconductor device, comprising:
- a strain layer formed over n-type transistors and p-type transistors formed on a silicon substrate;
- and
- a first shallow-trench-isolation oxide around each of the n-type transistors and a second shallow-trench-isolation oxide around each of the p-type transistors,
- wherein an upper surface of the first shallow-trench-isolation oxide of the n-type transistors is at a level different than a level of an upper surface of the second shallow-trench-isolation oxide of the p-type transistors.
Dependencies are inferred from the claim text.