US 9,006,823 B2Granted

Semiconductor device and method of manufacturing semiconductor device

AssigneeToyota Jidosha Kabushiki Kaisha

InventorShinya Yamazaki

Life of this patent

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Abstract

A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film. A thickness of the second region in a depth direction is gradually increased from the peripheral part of the element region to the central part thereof

Claims3

Dependent claims

A semiconductor device comprising:

a semiconductor substrate formed with an element region;
a first conductive type first region that is formed in the element region and located on a surface side of the semiconductor substrate;
a second conductive type second region that is located in a deeper position than the first region in the element region and contacts the first region;
a first conductive type third region that is located in a deeper position than the second region in the element region, contacts the second region, and is separated from the first region by the second region;
and
a gate that is disposed in a trench extending from the surface of the semiconductor substrate to reach the third region and contacts a range of the second region that separates the first region from the third region via an insulation film, wherein
a thickness of the second region in a depth direction is gradually increased from a peripheral part of the element region to a central part of the element region.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/166,031Filed 28 Jan 2014
Priority: JP 2013-01694331 Jan 2013
Published: US 2014/0210001 A131 Jul 2014
Granted: 14 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10P 32/00
Diffusion of dopants within, into or out of wafers, substrates or parts
H10D 12/038
Of vertical IGBTs: having a recessed gate, e.g. trench-gate IGBTs
H10D 12/481
Having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions: having gate…
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes

Family

US 2014/0210001 A1Pre-grant publication · published 31 Jul 2014
US 9,006,823 B2This patent

From the US filing history. Foreign family members aren’t listed.

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