Semiconductor test and monitoring structure to detect boundaries of safe effective modulus

An integrated circuit (IC) chip test structure comprising:

• an IC chip having a plurality of layers, at least two of the plurality of layers being metal layers;
• a plurality of solder bump pads on the IC chip;
• a plurality of solder bumps, each of the plurality of solder bumps being positioned on a corresponding one of the plurality of solder bump pads;
• and
• a plurality of monitor chains, each of the plurality of monitor chains being proximate to one of the plurality of solder bump pads, wherein each of the plurality of monitor chains comprises at least two metal via stacks extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip electrically isolated from the corresponding one of the plurality of solder bump pads, such that each of the plurality of monitor chains forms a continuous circuit proximate to and electrically isolated from the corresponding one of the plurality of solder bump pads, and where the at least two metal via stacks are positioned substantially underneath the corresponding one of the plurality of solder bump;
• wherein the lower metal layer of each of the plurality of monitor chains is of a different metal density.