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US 9,006,114 B2Granted
Method for selectively removing a spacer in a dual stress liner approach
AssigneeAdvanced Micro Devices, Inc.
InventorsKai Frohberg, Volker Grimm, Heike Salz, Heike Berthold
Life of this patent
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Abstract
By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.
Claims22
A method, comprising:
- forming a dielectric layer stack above a first transistor and a second transistor, said dielectric layer stack comprising a first stress-inducing layer and an etch control layer formed above said first stress-inducing layer;
- performing an etch sequence for selectively removing a portion of said dielectric layer stack from above said second transistor;
- concurrently recessing metal silicide regions in the second transistor and reducing a size of sidewall spacer structure formed on sidewalls of a gate electrode structure of said second transistor, while maintaining a sidewall spacer structure formed on sidewalls of a gate electrode structure of said first transistor;
- forming a second stress-inducing layer above said first and second transistors;
- and
- removing a portion of said second stress-inducing layer from above said first transistor by using said etch control layer as an etch stop material.
3 more elements
A method, comprising:
- performing an etch sequence for selectively removing a portion of dielectric layer stack from above a first transistor while retaining a portion of the dielectric layer stack above a second transistor, said dielectric layer stack comprising a first stress-inducing layer and an etch control layer formed above said first stress-inducing layer;
- reducing a size of a sidewall space structure formed on sidewalls of a gate electrode structure of the first transistor, said reducing being concurrent with forming recesses in metal silicide regions in the first transistor, while maintaining a sidewall space structure formed on sidewalls of a gate electrode structure of the second transistor;
- forming a second stress-inducing layer above the reduced sidewall spacer structure and in the recesses of the first transistor.
Dependencies are inferred from the claim text.