Method for reducing interfacial layer thickness for high-k and metal gate stack

A method of forming a semiconductor device, the method comprising:

• performing an annealing process on an interfacial layer over a semiconductor substrate, the annealing process comprising:
• supplying a gas flow rate ranging from 10 sccm to 5 slm, wherein the gas comprises inert gas;
• and
• heating the interfacial layer at a temperature less than or equal to 600° C., wherein heating the interfacial layer comprises heating the interfacial layer having a capacitive effective thickness of about 1.37 nanometers (nm).

A method of forming a semiconductor device, the method comprising:

• performing an ultraviolet (UV) curing process on an interfacial layer over a semiconductor substrate, the UV curing process comprising:
• flowing an inert gas over the interfacial layer at a rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm);
• heating the interfacial layer at a temperature less than or equal to 700° C.;
• and
• etching the interfacial layer using vaporized hydrofluoric acid prior to flowing the inert gas over the interfacial layer.