US 9,006,049 B2Granted

Fabricating photonics devices fully integrated into a CMOS manufacturing process

AssigneeInternational Business Machines Corporation

InventorsSolomon Assefa, William M. J. Green, Yurii A. Vlasov, Min Yang

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Abstract

Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide and a germanium photodetector. The germanium photodetector may utilize a seeded crystallization from melt process so there is more flexibility in the processing of the germanium photodetector.

Claims17

Dependent claims

A method of incorporating a photonics device into a CMOS manufacturing process flow comprising:

providing a semiconductor substrate wherein the semiconductor substrate is a semiconductor on insulator substrate comprising a semiconductor material layer on a buried oxide layer;
processing a first portion of the semiconductor substrate to form a CMOS device according to a CMOS manufacturing process flow comprising:
patterning the semiconductor material layer in the semiconductor substrate to form first trenches between first pillars of semiconductor material;
filling the first trenches with an insulator material;
well and Vt implanting;
forming a gate structure;
forming source and drain implants;
and
forming contacts;
and
processing a second portion of the semiconductor substrate according to a process flow for a photonics device comprising:
patterning a semiconductor material layer in the semiconductor substrate to form second trenches between second pillars of semiconductor material;
filling the second trenches with an insulator material;
depositing a dielectric material over the second portion;
opening a window in the dielectric material to expose an underlying second pillar of semiconductor material;
depositing a layer of germanium over the first and second portions including over the dielectric material;
depositing a first insulating layer over the germanium layer;
patterning the germanium layer and first insulating layer over the second portion and removing the germanium layer and first insulating layer from the first portion;
and
depositing a nitride layer over the germanium layer and first insulating layer so as to encapsulate the germanium layer and first insulating layer;
and
wherein the process steps of patterning a semiconductor material layer through depositing a nitride layer over the germanium layer in the processing the second portion of the semiconductor substrate occur after filling the first trenches with an insulator material in the processing the first portion of the semiconductor substrate;
and
processing the second portion of the semiconductor substrate further comprising:
opening the first insulating layer and the nitride layer to form an opening;
depositing an oxide material over the first and second portions and in the opening;
and
depositing a metallic material to make contact with the germanium layer.

25 more elements

A method of incorporating a photonics device into a CMOS manufacturing process flow comprising:

providing a semiconductor substrate wherein the semiconductor substrate is a semiconductor on insulator substrate comprising a semiconductor material layer on a buried oxide layer;
processing a first portion of the semiconductor substrate to form a CMOS device according to a CMOS manufacturing process flow comprising:
patterning the semiconductor material layer in the semiconductor substrate to form first trenches between first pillars of semiconductor material;
filling the first trenches with an insulator material;
well and Vt implanting;
forming a gate structure;
forming source and drain implants;
and
forming contacts;
and
processing a second portion of the semiconductor substrate according to a process flow for a photonics device comprising:
patterning a semiconductor material layer in the semiconductor substrate to form second trenches between second pillars of semiconductor material;
filling the second trenches with an insulator material;
depositing a dielectric material over the second portion;
opening a window in the dielectric material to expose an underlying second pillar of semiconductor material;
depositing a layer of germanium over the first and second portions including over the dielectric material;
depositing a first insulating layer over the germanium layer;
patterning the germanium layer and first insulating layer over the second portion and removing the germanium layer and first insulating layer from the first portion;
and
depositing a nitride layer over the germanium layer and first insulating layer so as to encapsulate the germanium layer and first insulating layer;
and
processing the second portion of the semiconductor substrate during the forming contacts step in the processing the first portion, further comprising:
opening the first insulating layer and the nitride layer in a first area to expose a first area of the germanium layer;
implanting a dopant in the first area of the germanium layer;
opening the first insulating layer and the nitride layer in a second area to expose a second area of the germanium layer;
and
implanting a second dopant in the second area of the germanium layer.

24 more elements

A method of incorporating a photonics device into a CMOS manufacturing process flow comprising:

providing a semiconductor substrate;
processing a first portion of the semiconductor substrate to form a CMOS device according to a CMOS manufacturing process flow comprising;
patterning the semiconductor material layer in the semiconductor substrate to form first trenches between first pillars of semiconductor material;
filling the first trenches with an insulator material;
well and Vt implanting;
forming a gate structure;
forming source and drain implants;
and
forming contacts;
and
processing a second portion of the semiconductor substrate according to a process flow for a first photonics device comprising:
patterning a semiconductor material layer in the semiconductor substrate to form second trenches between second pillars of semiconductor material;
filling the second trenches with an insulator material;
low dose implanting at least one of the second pillars to form a pn or p-i-n junction;
high dose implanting at least another one of the second pillars to form a low resistance contact;
and
processing a third portion of the semiconductor substrate according to a process flow for a second photonics device comprising:
patterning a semiconductor material layer in the semiconductor substrate to form third trenches between third pillars of semiconductor material;
filling the third trenches with an insulator material;
depositing a dielectric material over the third portion;
opening a window in the dielectric material to expose an underlying third pillar of semiconductor material;
depositing a layer of germanium over the first and third portions including over the dielectric material;
depositing a first insulating layer over the germanium layer;
patterning the germanium layer and first insulating layer over the third portion and removing the germanium layer and first insulating layer from the first portion;
and
depositing a nitride layer over the germanium layer and first insulating layer so as to encapsulate the germanium layer and first insulating layer;
wherein the process steps of patterning a semiconductor material layer through depositing a nitride layer over the germanium layer in the processing the third portion of the semiconductor substrate occur after filling the first trenches with an insulator material in the processing of the first portion of the semiconductor substrate;
and
processing the third portion of the semiconductor substrate further comprising:
opening the first insulating layer and the nitride layer to form an opening;
depositing an oxide material over the first and third portions and in the opening;
and
depositing a metallic material to make contact with the germanium layer in the third portion.

30 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/085,752Filed 20 Nov 2013 · division
Priority: 22 Nov 2010
Published: US 2014/0080269 A120 Mar 2014
Granted: 14 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
G02B 6/136
Integrated optical circuits characterised by the manufacturing method: by etching
H10D 84/0165
The components including insulated gates, e.g. IGFETs: the components including complementary IGFETs, e.g. CMOS devices
H10F 30/221
The devices having only one potential barrier, e.g. photodiodes: the potential barrier being a PN homojunction

Family

Application12/951,597Parent of this division · filed 22 Nov 2010
US 2014/0080269 A1Pre-grant publication · published 20 Mar 2014
US 8,633,067 B2Parent of this division
US 2012/0129302 A1Published application
US 9,006,049 B2This patent

From the US filing history. Foreign family members aren’t listed.

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