Mask assignment optimization

A physical computing system comprising:

• a processor;
• and
• a memory comprising machine readable instructions that when executed by the processor, cause the system to:
• determine a first subset of critical vias from a set of vias to be formed between two metal layers, the first subset of vias based on a via-to-metal-line distance such that each via of the first subset of critical vias is to be spaced less than the via-to-metal-line distance from a corresponding non-interacting metal line;
• determine overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias;
• and
• set both the alignment tree and mask assignment for the vias so as to maximize a placement of vias from the first subset of critical vias on a mask that has less overlay control error to the mask forming the corresponding non-interacting metal lines.

A method for fabricating metal and via layers in an integrated circuit, the method comprising:

• forming a first metal layer using a first group of masks;
• forming a second metal layer using a second group of masks;
• and
• forming critical and non-critical vias between the first and second metal layers using a third group of masks, wherein a first subset of critical vias are vias within a predetermined distance from a non-interacting metal line and a second subset of critical vias are vias interacting with a metal line that is narrower than a predetermined width;
• wherein the three groups of masks are aligned to each other and a pattern division among masks is set so as to maximize a placement of critical vias on masks where there is less overlay control error to masks forming the metal lines relevant to the critical vias.