US 9,003,256 B2 · System and method for testing integrated circuits by determining the solid timing window

Abstract

Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, and the solid operating timing window used to determine a key timing index. A method for determining the solid operating timing window is disclosed. A plurality of sets of operating parameters is generated. For each of the plurality of sets of operating parameters, the respective set of operating parameters is applied to a test environment. The integrated circuit is then operated under the applied respective set of operating parameters. A determining a data valid window is determined for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of sets of operating parameters, where the solid operating timing window is defined as the logical intersection of the determined data valid windows such that the integrated circuit will return valid sample.

Claims36

Dependent claims

A method for testing an integrated circuit, the method comprising:

generating a plurality of sets of operating parameters;
for each of the plurality of sets of operating parameters:
applying a respective set of operating parameters to a test environment;
operating the integrated circuit in the test environment;
and
determining a data valid window for the integrated circuit for the respective set of operating parameters;
and
when the data valid windows have been determined for the plurality of sets of operating parameters, the data valid windows defining a set of determined data valid windows;
determining a solid operating timing window for the integrated circuit from the set of determined data valid windows whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging to the set of determined data valid windows such that the integrated circuit will return a valid sample;
and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of determined data valid windows.

7 more elements

A method of testing an integrated circuit, the method comprising:

generating a plurality of sets of operating parameters;
for each of the plurality of sets of operating parameters:
applying a respective set of operating parameters to a test environment;
operating the integrated circuit in the test environment;
generating a plurality of test data;
generating a first clock signal having a first frequency and a first phase;
generating a plurality of second clock signals, each of the plurality of second clock signals having the first frequency and one of a plurality of second phases;
for each of the plurality of test data and for each of the plurality of second clock signals:
transmitting the respective test data and the first clock signal to the integrated circuit;
receiving a data signal from the integrated circuit;
capturing the data signal received from the integrated circuit in digital form by sampling the at least one data signal using the respective second clock signal of the plurality of second clock signals;
comparing the data signal when captured in digital form with a reference pattern associated with the respective test data;
determining a result from the comparing, wherein the result is associated with both the respective test data and the respective second clock signal having one of the plurality of second phases;
and
identifying a data valid window for the integrated circuit for the applied set of operating parameters from the said results determined for the plurality of test data and the plurality of second clock signals;
and
when the data valid windows have been identified for the plurality of sets of operating parameters, the data valid windows defining a set of identified data valid windows:
determining a solid operating timing window for the integrated circuit from the set of identified data valid windows, whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging to the set of identified data valid windows such that the integrated circuit will return a valid sample and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of identified data valid windows.

15 more elements

A system for testing an integrated circuit, the system comprising:

a test environment for operating the integrated circuit, the test environment having:
a program memory for storing instructions;
a microprocessor for retrieving instructions from the program memory, the microprocessor configured to:
instruct an operating parameter controller to apply the set of operating parameters to the test environment and send a test data to a controller;
and
a controller for converting the test data between a digital form and an electrical waveform;
wherein the system is configured to:
generate a plurality of sets of operating parameters;
for each of the sets of operating parameters:
apply the respective set of operating parameters to the test environment;
operate the integrated circuit, using the test data, in the test environment;
and
determine a data valid window for the integrated circuit for the set of operating parameters;
and
when the data valid windows have been determined for the plurality of sets of operating parameters, the data valid windows defining a set of determined data valid windows:
determine a solid operating timing window for the integrated circuit from the set of determined data valid windows, whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging to the set of determined data valid windows such that the integrated circuit will return a valid sample, and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of determined data valid windows.

13 more elements

A system for testing an integrated circuit, the system comprising:

a test environment for operating the integrated circuit, the test environment having:
a program memory for storing instructions;
a microprocessor for retrieving from the program memory, the microprocessor configured to:
instruct an operating parameter controller to apply the set of operating parameters to the test environment, and
send a test data to a controller;
and
the controller for converting the test data between a digital form and an electrical waveform;
wherein the system is configured to:
generate a plurality of sets of operating parameters;
for each of the plurality of sets of operating parameters:
apply the set of operating parameters to the test environment;
operate the integrated circuit in the test environment under the set of operating parameters;
generate a plurality of test data;
generate a first clock signal having a first frequency and a first phase;
generate a plurality of second clock signals, each of the plurality of second clock signals having the first frequency and one of a plurality of second phases;
for each of the plurality of test data and for each of the plurality of second clock signals:
transmit the respective test data and the first clock signal to the integrated circuit;
receive a data signal from the integrated circuit;
capture the data signal received from the integrated circuit in digital form by sampling the at least one data signal using the respective second clock signal of the plurality of second clock signals;
compare the data signal when captured in digital form with a reference pattern associated with the respective test data;
determine a result from the comparing, wherein the result is associated with both the respective test data and the respective second clock signal having one of the plurality of second phases;
and
identify a data valid window for the set of operating parameters for the integrated circuit from the said results determined for the plurality of test data and the plurality of second clock signals;
and
when the data valid windows have been identified for the plurality of sets of operating parameters, the data valid windows defining a set of identified data valid windows:
determine a solid operating timing window for the integrated circuit from the set of identified data valid windows, whereby the solid operating timing window is defined as a logical intersection of the data valid windows belonging in to the set of identified data valid windows such that the integrated circuit will return a valid sample and no solid operating timing window is defined where there is no logical intersection of the data valid windows belonging to the set of identified data valid windows.

23 more elements

Dependencies are inferred from the claim text.

System and method for testing integrated circuits by determining the solid timing window

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System and method for testing integrated circuits by determining the solid timing window

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Abstract

Claims36