US 9,003,159 B2Granted

Data caching in non-volatile memory

AssigneeMarvell World Trade Ltd.

InventorsShekhar S. Deshkar, Sandeep Karmarkar, Arvind Pruthi, Ram Kishore Johri

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Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, can perform data caching. In some implementations, a method and system include receiving information that includes a logical address, allocating a physical page in a non-volatile memory structure, mapping the logical address to a physical address of the physical page, and writing, based on the physical address, data to the non-volatile memory structure to cache information associated with the logical address. The logical address can include an identifier of a data storage device and a logical page number.

Claims11

Dependent claims

An apparatus, comprising:

a flash memory structure;
circuitry to receive a command sequence that includes a logical address, wherein the logical address includes (i) information that identifies a data storage device from among two or more separate data storage devices and (ii) a logical page number within the identified data storage device;
circuitry to receive data associated with the logical address;
circuitry to allocate a physical page in the flash memory structure;
circuitry to store a mapping from the logical address to a physical address associated with the physical page;
circuitry to write, based on the physical address, the data associated with the logical address to the flash memory structure to cache the data associated with the logical address;
and
circuitry to (i) invalidate the physical page in the flash memory structure based on the logical address being included in an invalidate command sent by an application to indicate caching of the data associated with the logical address is no longer needed and (ii) allow a garbage collector to directly use the physical page when performing an erasure to make the physical page available for re-allocation;
wherein the mapping indicates a cached status of the data associated with the logical address;
and
wherein the mapping goes from the logical address to the physical address without an intervening reference to a logical page number (LPN) of the flash memory structure.

8 more elements

A method, comprising:

receiving, from a host system, information that includes a logical address, wherein the logical address comprises (i) a target device identifier for one of two or more separate data storage devices and (ii) a logical block address (LBA) within a single data storage device identified by the target device identifier;
receiving data associated with the logical address from one of the host system or a data storage device of the two or more separate data storage devices;
allocating a physical page in a flash memory structure, wherein the flash memory structure is configured to cache data for the two or more separate data storage devices;
storing a mapping from the logical address to a physical address of the physical page;
writing, based on the physical address, the data associated with the logical address to the flash memory structure to cache the data associated with the logical address;
invalidating the physical page in the flash memory structure based on the logical address being included in an invalidate command sent by an application to indicate caching of the data associated with the logical address is no longer needed;
and
allowing a garbage collector to directly use the physical page when performing an erasure to make the physical page available for re-allocation;
wherein the mapping indicates a cached status of the data associated with the logical address;
and
wherein the mapping goes directly from the logical address to the physical address.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/898,483Filed 5 Oct 2010 · us provisional application
Priority: 5 Oct 2009
Published: US 2011/0082967 A17 Apr 2011
Granted: 7 Apr 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 12/0873
For peripheral storage systems, e.g. disk cache: mapping of cache memory to specific storage devices or parts thereof
G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/0292
User address space allocation, e.g. contiguous or non contiguous base addressing: using tables or multilevel address translation means
G06F 2212/222
Employing cache memory using specific memory technology: non-volatile memory

Family

Application61/248,845Us provisional application · filed 5 Oct 2009
US 2011/0082967 A1Pre-grant publication · published 7 Apr 2011
US 9,003,159 B2This patent

From the US filing history. Foreign family members aren’t listed.

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