Clock synthesis systems, circuits and methods

A clock synthesis system, comprising:

• a frequency synthesis circuit that divides a source clock by different integer values in response to at least a difference between the source clock and a synchronous clock to generate a reference clock, wherein the reference clock is an audio clock capable of being used to process audio data;
• and
• a multiplier circuit that generates at least one output clock by frequency multiplying the reference clock, wherein the frequency multiplying of the reference clock is performed by a phase lock loop (PLL) circuit after the division of the source clock;
• and wherein
• the synchronous clock is slower than the source clock and the reference clock, and the at least one output clock is a rational multiple of, and synchronous with, the synchronous clock.

A method, comprising:

• dividing a source clock by multiple integer values based on a select signal to generate a reference clock signal that is synchronous with, and a rational multiple of, a synchronization pulse input;
• modulating the select signal in response to at least a difference value generated in response to a difference between the synchronization pulse input and the source clock;
• and
• frequency multiplying and filtering the reference clock signal to generate an output signal, wherein the frequency multiplying and filtering of the reference clock signal is performed by a phase lock loop (PLL) circuit after the dividing of the source clock and the modulating of the select signal.