Method of burn-in test of EEPROM or flash memories

An integrated circuit, comprising:

• first, second, third, and fourth high voltage MOS transistors electrically coupled to each other;
• and
• a test circuit configured to test the high voltage MOS transistors by:
• performing a first burn-in test that includes subjecting, to a first test voltage, gate oxides of the first and second high voltage MOS transistors in a conductive state, and subjecting, to a second test voltage, the third and fourth high voltage MOS transistors in a blocked state, the first test voltage being set to a value higher than a high supply voltage to be supplied to the high voltage MOS transistors in a normal operating mode, the second test voltage being set to a value lower than the first test voltage and sufficient to ensure a normal operation of the circuit;
• changing the states of the high voltage transistors;
• and
• performing a second burn-in test that includes subjecting, to the first test voltage, gate oxides of the third and fourth high voltage MOS transistors in the conductive state, and subjecting, to the second test voltage, the first and second high voltage MOS transistors in the blocked state.

An integrated circuit, comprising:

• a latch including first and second latch legs, the first latch leg including a first PMOS transistor and a first NMOS transistor electrically coupled between first and second supply terminals and electrically coupled to each other by a first intermediate node, the second latch leg including a second PMOS transistor and a second NMOS transistor electrically coupled between third and fourth supply terminals and electrically coupled to each other by a second intermediate node, the first intermediate node being electrically coupled to respective gates of the second PMOS transistor and the second NMOS transistor, and the second intermediate node being electrically coupled to respective gates of the first PMOS transistor and the first NMOS transistor;
• and
• a test circuit configured to supply the first and third supply terminals with first and second test voltages during a burn-in test mode and supply the first and third supply terminals with a same first supply voltage during a normal operating mode, wherein the test circuit includes:
• a generation circuit configured to generate a high supply voltage;
• a switching circuit configured to receive the high supply voltage from the generation circuit, provide the first and second test voltages based on the high supply voltage, the second test voltage being lower than the first test voltage;
• and,
• a control circuit configured to cause the generating circuit to cause the switching circuit to transmit the first and second test voltages to the respective source terminals of the first and second high voltage P-channel MOS transistors as a function of the conductive or blocked state of the first and second high voltage P-channel MOS transistors.