ESD protection circuit
AssigneeMediatek Inc.
InventorChien-Hui Chuang
Life of this patent
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Abstract
An electrostatic discharge (ESD) protection circuit is provided. A first NMOS transistor is coupled to a power line. A second NMOS transistor is coupled between the first transistor and a ground. A detection unit provides a detection signal when an ESD event occurs at the power line. A trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors.
Claims15
An electrostatic discharge (ESD) protection circuit, comprising:
- a first NMOS transistor coupled to a power line;
- a second NMOS transistor coupled between the first transistor and a ground;
- a detection unit, providing a detection signal when an ESD event occurs at the power line;
- and
- a trigger unit, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors,
- wherein the detection unit comprises:
- a first resistor coupled between the power line and a gate of the first NMOS transistor;
- a second resistor coupled between the gate of the first NMOS transistor and the ground;
- a third resistor coupled to the power line;
- and
- a diode, having an anode coupled to the ground and a cathode coupled to the third resistor.
An electrostatic discharge (ESD) protection circuit, comprising:
- a first diode, having an anode coupled to a pad and a cathode coupled to a power line;
- a first NMOS transistor coupled to the pad;
- a second NMOS transistor coupled between the first transistor and a ground;
- a detection unit coupled between the power line and the ground, providing a detection signal when an ESD event occurs at the pad;
- a trigger unit coupled between the power line and the ground, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a first discharge path is formed from the pad to the ground through the first and second NMOS transistors.
Dependencies are inferred from the claim text.