Transistor test structure

A test structure comprising:

• a plurality of test pads comprising at least one first test pad, and at least one common test pad;
• a direct current (DC) test structure comprising a test transistor, and a first plurality of transistors, said test transistor coupled to said at least one first test pad, and said at least one common test pad, said DC test structure configured to test at least one DC property of said test transistor;
• and
• an alternating current (AC) test structure comprising a second plurality of transistors adjacent said test transistor, said AC test structure coupled to said test transistor, and said at least one common test pad, said AC test structure configured to test at least one AC property of said test transistor;
• said test transistor and each of said second plurality of transistors comprising a conduction terminal coupled to said at least one common test pad;
• said first plurality of transistors being uncoupled to said at least one common test pad and said at least one first test pad, and configured to provide conformity transistors for said DC test structure.

A semiconductor wafer comprising:

• a plurality of semiconductor dies;
• at least one of said plurality of semiconductor dies comprising at least one test structure comprising
• a plurality of test pads comprising at least one first test pad, and at least one common test pad,
• a direct current (DC) test structure comprising a test transistor, said DC test structure coupled to said at least one first test pad, and said at least one common test pad, and configured to test at least one DC property of said test transistor, and
• an alternating current (AC) test structure comprising a plurality of transistors adjacent said test transistor, said AC test structure coupled to said test transistor, and said at least one common test pad, said AC test structure configured to test at least one AC property of said test transistor,
• said test transistor and each of said plurality of transistors comprising a control terminal coupled to said at least one common test pad,
• said plurality of transistors configured to provide conformity transistors shared by said AC test structure and said DC test structure.

A semiconductor wafer comprising:

• a plurality of semiconductor dies;
• at least one of said plurality of semiconductor dies comprising at least one test structure comprising
• a plurality of test pads comprising at least one first test pad, and at least one common test pad,
• a direct current (DC) test structure comprising a test transistor, and a first plurality of transistors, said test transistor coupled to said at least one first test pad, and said at least one common test pad, said DC test structure configured to test at least one DC property of said test transistor, and
• an alternating current (AC) test structure comprising a second plurality of transistors adjacent said test transistor, said AC test structure coupled to said test transistor, and said at least one common test pad, said AC test structure configured to test at least one AC property of said test transistor,
• said test transistor and each of said second plurality of transistors comprising a conduction terminal coupled to said at least one common test pad,
• said first plurality of transistors being uncoupled to said at least one common test pad and said at least one first test pad, and configured to provide conformity transistors for said DC test structure.

A testing method comprising:

• coupling a test apparatus to a test structure comprising
• a plurality of test pads comprising at least one first test pad, and at least one common test pad,
• a direct current (DC) test structure comprising a test transistor, said DC test structure being coupled to the at least one first test pad, and the at least one common test pad, and configured to test at least one DC property of the test transistor, and
• an alternating current (AC) test structure comprising a plurality of transistors adjacent the test transistor, the AC test structure coupled to the test transistor, and the at least one common test pad, the AC test structure configured to test at least one AC property of the test transistor,
• the test transistor and each of the plurality of transistors comprising a control terminal coupled to the at least one common test pad,
• the plurality of transistors providing conformity transistors shared by the AC test structure and the DC test structure;
• and
• operating the test apparatus to apply a DC test program to the test structure, and to apply an AC test program to the test structure.

A test method comprising:

• coupling a test apparatus to a test structure comprising
• a plurality of test pads comprising at least one first test pad, and at least one common test pad,
• a direct current (DC) test structure comprising a test transistor, and a first plurality of transistors, said test transistor coupled to the at least one first test pad, and the at least one common test pad, the DC test structure configured to test at least one DC property of the test transistor, and
• an alternating current (AC) test structure comprising a second plurality of transistors adjacent the test transistor, the AC test structure coupled to the test transistor, and the at least one common test pad, the AC test structure configured to test at least one AC property of the test transistor,
• the test transistor and each of the second plurality of transistors comprising a conduction terminal coupled to the at least one common test pad,
• the first plurality of transistors being uncoupled to the at least one common test pad and the at least one first test pad, and configured to provide conformity transistors for the DC test structure;
• and
• operating the test apparatus to apply a DC test program to the test structure, and to apply an AC test program to the test structure.