Back to results
US 9,000,529 B1Granted
Reduction of single event upsets within a semiconductor integrated circuit
AssigneeXilinx, Inc.
InventorsPraful Jain, James Karp, Michael J. Hart, Ramakrishna K. Tanikella
Life of this patent
Estimating the term…
Abstract
A circuit includes a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate and an n-well implemented within the p-type substrate that is independent of the storage element. The n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well.
Claims18
A circuit, comprising:
- a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate;
- and
- an n-well implemented within the p-type substrate that is independent of the storage element;
- wherein the n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well;
- wherein the n-well is separated from the storage element by a region of the p-type substrate;
- and
- wherein the circuit further comprises at least one mitigating circuit element within the region.
4 more elements
A semiconductor integrated circuit, comprising:
- a p-type substrate;
- a complimentary metal-oxide semiconductor (CMOS) storage element implemented within the p-type substrate;
- and
- an n-well implemented within the p-type substrate that is independent of the storage element;
- wherein the n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well;
- wherein the n-well is separated from the storage element by a region of the p-type substrate;
- and
- wherein the circuit further comprises at least one mitigating circuit element within the region.
5 more elements
A method of circuit design layout, comprising:
- identifying a complimentary metal-oxide semiconductor (CMOS) storage element implemented within a p-type substrate within a circuit design;
- selecting an n-well within the p-type substrate that is closest to the storage element and independent of the storage element;
- determining, using a processor, whether the n-well and the storage element are separated by a minimum distance in which the p-type substrate includes no n-well;
- wherein the n-well is separated from the storage element by a region of the p-type substrate;
- wherein the region includes at least one mitigating circuit element;
- and
- indicating whether a design rule is violated according to the determining.
4 more elements
Dependencies are inferred from the claim text.