Local interconnects for field effect transistor devices

A multi-field effect transistor (FET) device comprising:

• a first FET device arranged on a substrate, the first FET device including a first active region and a second active region;
• a second FET device arranged on the substrate, the second FET device including a first active region and a second active region;
• a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device;
• a first conductive via arranged proximate to a first distal end of the first conductive interconnect, the first conductive via in contact with the first conductive interconnect in a portion of the first conductive interconnect having the first cross sectional area;
• a second conductive interconnect electrically connecting the second active region of the first FET device to the second active region of the second FET device, the second conductive interconnect having a first cross sectional area proximate to the second active region of the first FET device that is greater than a second cross sectional area proximate to the second active region of the second FET device;
• a second conductive via arranged proximate to a first distal end of the second conductive interconnect, the second conductive via in contact with the second conductive interconnect in a portion of the second conductive interconnect having the first cross sectional area;
• a third conductive via in contact with a gate stack of the first and the second FET devices,
• wherein the first, second, and third conductive vias are contact points where a voltage is applied to the first and second FETs of the multi-field effect transistor device.