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US 8,995,174 B2Granted
Semiconductor integrated circuit
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorJun Koyama
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes NAND gates and switches to form a circuit to hold data, and a capacitor electrically connected to the circuit via a transistor to store the data held in the circuit. The transistor has a channel formation region including an oxide semiconductor.
Claims19
A semiconductor device comprising:
- a first NAND gate comprising a first input terminal, a second input terminal, and an output terminal;
- a second NAND gate comprising a first input terminal, a second input terminal, and an output terminal;
- a switch comprising a first terminal and a second terminal;
- a transistor comprising a first terminal, a second terminal, and a gate;
- and
- a capacitor comprising a first terminal and a second terminal,
- wherein the output terminal of the first NAND gate is electrically connected to the first terminal of the switch,
- wherein the second terminal of the switch is electrically connected to the first input terminal of the second NAND gate,
- wherein the output terminal of the second NAND gate is electrically connected to the first input terminal of the first NAND gate and the first terminal of the transistor,
- wherein the second terminal of the transistor is electrically connected to the first terminal of the capacitor, and
- wherein the transistor comprises a channel formation region comprising an oxide semiconductor.
8 more elements
A Semiconductor device comprising:
- a first NAND gate comprising a first input terminal, a second input terminal, and an output terminal;
- a second NAND gate comprising a first input terminal, a second input terminal, and an output terminal;
- a first switch comprising a first terminal and a second terminal;
- a third NAND gate comprising a first input terminal, a second input terminal, and an output terminal,
- a fourth NAND gate comprising a first input terminal, a second input terminal, and an output terminal,
- a second switch comprising a first terminal and a second terminal;
- a third switch comprising a first terminal and a second terminal;
- a transistor comprising a first terminal, a second terminal, and a gate;
- and
- a capacitor comprising a first terminal and a second terminal,
- wherein the output terminal of the first NAND gate is electrically connected to the first terminal of the first switch,
- wherein the second terminal of the first switch is electrically connected to the first input terminal of the second NAND gate and the first terminal of the third switch,
- wherein the output terminal of the second NAND gate is electrically connected to the first input terminal of the first NAND gate and the first terminal of the transistor,
- wherein the output terminal of the third NAND gate is electrically connected to the first terminal of the second switch,
- wherein the second terminal of the second switch is electrically connected to the first input terminal of the fourth NAND gate,
- wherein the output terminal of the fourth NAND gate is electrically connected to the first input terminal of the third NAND gate and the second terminal of the third switch,
- wherein the second terminal of the transistor is electrically connected to the first terminal of the capacitor, and
- wherein the transistor comprises a channel formation region comprising an oxide semiconductor.
15 more elements
A semiconductor device comprising:
- a sequential circuit comprising:
- a first NAND gate comprising a first input terminal, a second input terminal, and an output terminal;
- a second NAND gate comprising a first input terminal, a second input terminal, and an output terminal;
- a first switch comprising a first terminal and a second terminal;
- a first transistor comprising a first terminal, a second terminal, and a gate;
- and
- a capacitor comprising a first terminal and a second terminal;
- and
- a second transistor comprising a first terminal, a second terminal, and a gate,
- wherein the output terminal of the first NAND gate is electrically connected to the first terminal of the first switch,
- wherein the second terminal of the first switch is electrically connected to the first input terminal of the second NAND gate,
- wherein the output terminal of the second NAND gate is electrically connected to the first input terminal of the first NAND gate and the first terminal of the first transistor,
- wherein the second terminal of the first transistor is electrically connected to the first terminal of the capacitor,
- wherein the first terminal of the second transistor is electrically connected to the sequential circuit, and
- wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.
12 more elements
Dependencies are inferred from the claim text.