System, a method and a computer program product for electronic sub-integer frequency division

An electronic sub-integer frequency divider circuit, comprising:

• a phase rotator circuit configured to produce a first signal by rotatably outputting, at a rate determined by a control signal, one or more of a plurality of phase-shifted signals having a frequency fA, wherein the frequency of the first signal is determined by the frequency fA and by the control signal, and wherein the control signal is based on a primary regulating signal;
• a clock circuitry configured to process the first signal thereby producing a first clock signal and a second clock signal, wherein the second clock signal is different from the first clock signal;
• a pulse generator configured to:
• receive the first clock signal,
• receive the second clock signal,
• receive a control command,
• process, in accordance with the control command, the second clock signal and at least one M signal having a period TP, thereby producing a second regulating signal which includes S pulses in each period TP, wherein the period TP is longer than the period of the first clock signal and the period of the second clock signal, and
• process the second regulating signal and the first clock signal, thereby producing the primary regulating signal, wherein the primary regulating signal includes Q pulses in each period TP, and wherein Q is different from S;
• and
• an output interface configured to provide a sub-integer output signal whose frequency is responsive to the regulating signal.