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US 8,981,983 B2Granted
A/D conversion circuit, solid-state image sensor, and camera system
AssigneeSony Corporation
InventorYasuaki Hisamatsu
Life of this patent
Estimating the term…
Abstract
An A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system.
Claims21
An A/D conversion circuit comprising:
- a comparator that compares a signal potential with a reference voltage and outputs a determination signal based on the comparison;
- and
- a counter controlled in accordance with the determination signal,
- wherein the counter
- switches a count mode from an up count to a down count and from a down count to an up count while a count value is held,
- counts an input clock at a frequency two times as high as that of an input clock signal, and
- latches the input clock in accordance with an output signal of the comparator and sets non-inverted or inverted data of the latched data to be data of a least significant bit (LSB).
4 more elements
A solid-state image sensor comprising:
- pixel units in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
- and
- a pixel signal reading unit that reads pixel signals in units of a plurality of pixels from the pixel units,
- wherein,
- the pixel signal reading unit includes a plurality of A/D conversion circuits, and
- each A/D conversion circuit comprises (a) a comparator that compares a signal potential with a reference voltage and outputs a determination signal based on the comparison;
- and (b) a counter controlled in accordance with athe determination signal, the counter (1) switching a count mode from an up count to a down count and from a down count to an up count while a count value is held, (2) counting at both rising and falling edges of an input clock at a frequency two times as high as that of an input clock signal, and (3) latching the input clock in accordance with an output signal of the comparator and sets non-inverted or inverted data of the latched data to be data of a least significant bit (LSB).
4 more elements
A camera system comprising:
- a solid-state image sensor;
- and
- an optical system for forming a subject image in the image sensor, the solid-state image sensor including (a) pixel units in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix, and (b) a pixel signal reading unit that reads pixel signals in units of a plurality of pixels from the pixel units,
- wherein,
- the pixel signal reading unit includes a plurality of A/D conversion circuits, and
- each A/D conversion circuit includes each A/D conversion circuit comprises (a) a comparator that compares a signal potential with a reference voltage and outputs a determination signal based on the comparison;
- and (b) a counter controlled in accordance with the determination signal, the counter (1) switching a count mode from an up count to a down count and from a down count to an up count while a count value is held, (2) counting an input clock at a frequency two times as high as that of an input clock signal, and (3) latching the input clock in accordance with an output signal of the comparator and sets non-inverted or inverted data of the latched data to be data of a least significant bit (LSB).
4 more elements
Dependencies are inferred from the claim text.