Via structure for integrated circuits

An integrated circuit comprising:

• a silicon layer;
• a plurality of metal layers, wherein the plurality of metal layers includes a power plane, a ground plane, a first metal layer having a first plurality of signal lines and a second metal layer having a second plurality of signal lines, wherein each of the first plurality of signal lines has a greater vertical thickness than each of the second plurality of signal lines;
• a plurality of via structures each implemented in a corresponding predefined area of the integrated circuit, wherein each of the plurality of via structures includes:
• a first plurality of vias, wherein a center of each of the first plurality of vias extends along a vertical axis between the first metal layer and the silicon layer, and wherein each of the first plurality of vias provides an electrical connection between a corresponding one of the first plurality of signal lines and circuitry implemented in the silicon layer;
• and
• a second plurality of vias, wherein a center of each of second plurality of vias extends along a vertical axis between the second metal layer and the silicon layer, and wherein each of the second plurality of vias provides an electrical connection between a corresponding one of the second plurality of signal lines and circuitry implemented in the silicon layer;
• wherein the center of each of the first plurality vias is closer to a center of the corresponding predefined area than the center of each of the second plurality of vias.