Finfet with reduced parasitic capacitance

A semiconductor structure comprising a field effect transistor, said field effect transistor comprising:

• a plurality of semiconductor fins located on an insulator layer, wherein a body region is located within a portion of each semiconductor fin;
• a gate stack of a gate dielectric and a gate electrode straddling each of said body regions;
• an inner gate spacer laterally surrounding said gate stack and including first and second outer sidewalls straddling said plurality of semiconductor fins;
• source extension regions located on said plurality of semiconductor fins and in greater proximity to said first outer sidewall than to said second outer sidewall;
• drain extension regions located on said plurality of semiconductor fins and in greater proximity to said second outer sidewall than to said first outer sidewall;
• an outer gate spacer laterally surrounding said inner gate spacer;
• a contiguous raised source region contacting each of said source extension regions;
• and
• a contiguous raised drain region contacting each of said drain extension regions, wherein each surface of said source extension regions and said drain extension regions that contacts said inner gate spacer is not parallel to said first and second outer sidewalls of said inner gate spacer.

A method of forming a semiconductor structure comprising:

• forming a plurality of semiconductor fins on an insulator layer;
• forming a gate stack of a gate dielectric and a gate electrode over portions of said plurality of semiconductor fins;
• forming an inner gate spacer around said gate stack, wherein first and second outer sidewalls of said inner gate spacer straddle said plurality of semiconductor fins;
• forming source extension regions and drain extension regions on said plurality of semiconductor fins, wherein said source extension regions are formed in greater proximity to said first outer sidewall than to said second outer sidewall, and said drain extension regions are formed in greater proximity to said second outer sidewall than to said first outer sidewall;
• forming an outer gate spacer around said inner gate spacer;
• and
• forming a contiguous raised source region directly on said source extension regions and a contiguous raised drain region directly on said drain extension regions, wherein said source extension regions are formed on all top surfaces and sidewall surfaces of said plurality of semiconductor fins that are located farther away from said gate stack than said first outer sidewall.

A method of forming a semiconductor structure comprising:

• forming a plurality of semiconductor fins on an insulator layer;
• forming a gate stack of a gate dielectric and a gate electrode over portions of said plurality of semiconductor fins;
• forming an inner gate spacer around said gate stack, wherein first and second outer sidewalls of said inner gate spacer straddle said plurality of semiconductor fins;
• forming source extension regions and drain extension regions on said plurality of semiconductor fins, wherein said source extension regions are formed in greater proximity to said first outer sidewall than to said second outer sidewall, and said drain extension regions are formed in greater proximity to said second outer sidewall than to said first outer sidewall, wherein each surface of said source extension regions and said drain extension regions that contacts said inner gate spacer is formed at an orientation that is not parallel to said first and second outer sidewalls of said inner gate spacer;
• forming an outer gate spacer around said inner gate spacer;
• and
• forming a contiguous raised source region directly on said source extension regions and a contiguous raised drain region directly on said drain extension regions.