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US 8,946,787 B2Granted
Reduced charge transistor
AssigneeInfineon Technologies Austria AG
InventorsRalf Siemieniec, Cedric Ouvrard
Life of this patent
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Abstract
Representative implementations of devices and techniques provide a reduced charge transistor arrangement. The capacitance and/or charge of a transistor structure may be reduced by minimizing an overlap of a top gate with respect to a drain of the transistor.
Claims26
A transistor device, comprising:
- a drift region layer arranged on a substrate, the drift region layer including a first region and a second region, the substrate coupled to a drain;
- a back gate formed at the first region of the drift region layer;
- a channel overlying the back gate, the back gate to at least deplete the channel;
- a top gate overlying the channel, the top gate overlying at least a portion of the first region of the drift region layer without fully overlying the second region of the drift region layer.
1 more element
A transistor cell, comprising:
- a drift region arranged on a substrate;
- a first back gate region formed at a first part of the drift region and a second back gate region formed at a second part of the drift region, a third part of the drift region located between the first back gate region and the second back gate region, the third part of the drift region overlying a drain region;
- a first channel overlaying the first back gate region and a second channel overlaying the second back gate region;
- a first top gate overlaying the first channel and overlaying at least a portion of the first back gate region and a second top gate overlaying the second channel and overlaying at least a portion of the second back gate region, at least a portion of the third part of the drift region is not overlaid by either the first top gate or the second top gate.
1 more element
A method of forming a transistor, comprising:
- arranging a drift region layer on a substrate, the substrate coupled to a drain;
- forming a back gate on a portion of the drift region layer;
- forming a channel layer overlying the back gate, the back gate to at least deplete the channel;
- and
- forming a top gate over a portion of the channel layer, such that the top gate overlays the back gate, without fully overlaying the drift region layer and without fully overlaying the drain.
2 more elements
A transistor device, comprising:
- a drift region having a first type of doping;
- a pair of wells of a second type of doping formed within the drift region, each of the wells including a back gate, each of the wells electrically coupled to a source contact;
- a pair of top gates having the second type of doping and electrically coupled to a gate contact, the top gates layered over portions of the drift region that overlay the back gates and forming a pair of channels of the first type of doping, the channels formed between the back gates and the top gates and electrically coupled to the source contact, a portion of the drift region between the pair of wells not being overlaid by either of the pair of top gates.
Dependencies are inferred from the claim text.