Merged FinFETs and method of manufacturing the same

A method comprising:

• forming a plurality of FinFETs comprising a substrate, a plurality of fin bodies, and a gate formed over the plurality of fin bodies;
• doping the plurality of FinFETs;
• preparing the surface of the plurality of FinFETs for a metal;
• depositing a layer of metal on the surface of the plurality of fin bodies;
• annealing the layer of metal to form silicide;
• performing a metal deposition process to merge the plurality of FinFETs with the metal, wherein the metal deposition process includes depositing the metal on the substrate, the plurality of fin bodies and the gate to such a thickness that the metal fills each gap between the plurality of fin bodies completing physical contact between each fin body, the substrate and the gate;
• and
• doping source and drain regions through the metal,
• wherein the metal deposition process is selective to the silicide formed on the plurality of fin bodies;
• and
• the annealing the layer of metal is performed prior to the performing the metal deposition process.

A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a program module configured to form a plurality of FinFETs, the program module:

• forms plurality of fin bodies on a substrate;
• forms a gate structure over the plurality of fin bodies;
• forms a layer of metal on the plurality of fin bodies;
• anneals the layer of metal to form silicide;
• merges the fin bodies with a metal by depositing the metal on the plurality of fin bodies and the gate structure, wherein the metal is in electrical contact with the gate structure;
• and
• implants source and drain regions through the metal,
• wherein the annealing is performed prior to the merging.

A method comprising:

• forming a plurality of fin bodies on a substrate;
• forming a gate structure over the plurality of fin bodies;
• and
• merging the fin bodies with a metal by depositing the metal on the plurality of fin bodies and the gate structure, wherein the metal is in electrical contact with the gate structure;
• and implanting source and drain regions through the metal,
• wherein:
• the gate is formed from poly or metal that intersects a channel region of the plurality of fin bodies and is isolated electrically from the plurality of fin bodies by a gate dielectric layer;
• a spacer is deposited on sidewalls of the gate;
• the spacer is resistant to HF etching;
• the plurality of fin bodies undergo:
• an implantation process which includes implanting an extension dopant and halo dopant;
• and
• an activation annealing process;
• and
• after the activation annealing process, the plurality of fin bodies undergo a pre-silicide clean process using dilute HF.