Method and apparatus for improving triggering uniformity of snapback electrostatic discharge protection devices
AssigneeAltera Corporation
InventorsJeffrey T. Watt, Antonio Gallerano
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Abstract
An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.
Claims26
A method for fabricating metal oxide (MOS) transistors, the method comprising:
- forming an active region, between an area designated for a first array of transistors arranged in parallel in a first block and an area designated for a second array of transistors arranged in parallel in a second block without forming the active region between transistors in the first array of transistors and between transistors within the second array of transistors, wherein the active region resides separately from the first array of transistors and the second array of transistors and is physically isolated from any transistor in the first array of transistors and the second array of transistors, and wherein the active region is a single floating region without metallic connection to any other region, and wherein the active region resides between and is in direct contact with a shallow trench isolation region of the first array of transistors and a shallow trench isolation region of the second array of transistors.
A method for fabricating metal oxide (MOS) transistors, the method comprising:
- performing source drain implantation for a first array of transistors and a second array of transistors with a first type of material;
- and
- forming an active region between an area designated for the first array of transistors and an area designated for the second array of transistors during the source drain implantation without forming the active region between transistors in the first array of transistors and between transistors within the second array of transistors, wherein the active region is physically isolated from any transistor from the first array of transistors and the second array of transistors, and wherein the active region is a single floating region without metallic connection to any other region, and wherein the active region resides between and is in direct contact with a shallow trench isolation region of the first array of transistors and a shallow trench isolation region of the second array of transistors.
Dependencies are inferred from the claim text.