Layout determining for wide wire on-chip interconnect lines

A computer program product for determining a layout of an interconnect line to minimize dishing of wide copper metallization in an integrated circuit, the computer program product comprising:

• a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising:
• computer readable program code configured to:
• receive a required width for an interconnect line;
• determine a number Nslots of elongate apertures to be arranged across the width of the interconnect line as the largest integer not greater than ((w−Wlow)/(Wslot+Wlow)) where Wlow=Kslot*(Wmax−Wslot), wherein w is the width of the interconnect line, Wlow is a minimal value of a finger width, Wslot is s a width of slots, Wmax is a maximum threshold width of the interconnect line, and Kslot is a factor of less than 1 which defines an onset of slotting;
• and
• determine a number of shorts placed along a length of said interconnect line as a function of a maximal elongate aperture length, wherein if the length of said interconnect line exceeds a threshold multiple shorts are placed along said interconnect line in a symmetrical manner.