Methods for layout verification for polysilicon cell edge structures in FinFET standard cells

A method for fabricating an integrated circuit, comprising:

• defining a library of functions implemented as standard cells including finFET devices;
• in each standard cell, forming polysilicon dummy structures on cell edges overlying at least a portion of a fin of the finFET devices;
• defining a netlist schematic for each standard cell that includes a three terminal MOS device that corresponds to each of the polysilicon dummy structures;
• receiving a gate level netlist that defines a desired function to be implemented as an integrated circuit using the standard cells;
• forming a pre-layout schematic netlist using the standard cells, the pre-layout schematic netlist including a three terminal MOS device for each of the polysilicon dummy structures in the standard cells;
• using the gate level netlist, performing an automated placement and route process to create a layout netlist implementing the user defined function using the standard cells;
• performing a layout to implement the layout netlist on an integrated circuit;
• extracting a post-layout schematic netlist from the layout, the post-layout schematic netlist including a three-terminal MOS device corresponding to each polysilicon dummy structure in the layout, wherein for each shared polysilicon dummy structure, the post-layout extracted schematic netlist includes two three terminal MOS devices each having a gate terminal, a source terminal and a body terminal and the gate terminals are coupled to one another, and the body terminals are coupled to one another;
• comparing the pre-layout schematic netlist to the post-layout schematic netlist to obtain a compare result;
• and
• responsive to the compare results, fabricating an integrated circuit by forming a photomask generation output from the post-layout schematic.

A method for forming an integrated circuit, comprising:

• receiving a gate level netlist defining a function for the integrated circuit;
• defining a standard cell library of predetermined blocks formed using finFET standard cells, each of finFET standard cells comprising at least one semiconductor fin, at least one polysilicon gate, and dummy polysilicon structures at one or more cell edges, the dummy polysilicon structures overlying a portion of the at least one semiconductor fin;
• from the gate level netlist, forming a pre-layout schematic netlist using the standard cells, the pre-layout schematic netlist having a three terminal MOS device with a gate terminal, a source terminal and a body terminal for each of the dummy polysilicon structures;
• using the gate level netlist, performing automated placement and routing of the standard cells to implement the function for the integrated circuit, and providing a layout netlist;
• forming a layout for implementing the function on the integrated circuit using the standard cells;
• extracting using a computer a post-layout schematic netlist from the layout, the post-layout schematic netlist including a three terminal MOS device for each dummy polysilicon structure in the layout;
• and
• verifying the layout by performing a layout versus schematic compare that compares the pre-layout schematic netlist to the post-layout schematic netlist.