Semiconductor device with stressed fin sections
AssigneeGlobalfoundries Inc.
InventorsScott Luning, Frank Scott Johnson
Life of this patent
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Abstract
A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.
Claims20
A semiconductor device comprising:
- a first semiconductor fin structure and a second semiconductor fin structure, wherein each semiconductor fin structure is formed over a semiconductor material and includes an upper surface, a first major sidewall, a second major sidewall opposite the first major sidewall, a first end sidewall, and a second end sidewall opposite the first end sidewall, wherein a gap is defined between the second end sidewall of the first semiconductor fin structure the first end sidewall of the second semiconductor fin structure;
- a first gate structure formed over the first semiconductor structure;
- a first spacer formed over the first semiconductor structure and surrounding the first gate structure;
- a second gate structure formed over the second semiconductor structure;
- a second spacer formed over the second semiconductor structure and surrounding the second gate structure;
- and
- a stress/strain inducing material at least partially filling the gap and in contact with the second end sidewall of the first semiconductor fin structure and with the first end sidewall of the second semiconductor fin structure.
A semiconductor device comprising:
- a plurality of axially-aligned semiconductor fin sections created from a common semiconductor fin structure extending in a first direction, each of the semiconductor fin sections having an upper surface, a first major sidewall, a second major sidewall opposite the first major sidewall, a first end sidewall, and a second end sidewall opposite the first end sidewall, wherein gaps are defined between semiconductor fin sections, with each gap being bounded by the second end sidewall of a selected semiconductor fin structure and the first end sidewall of a respective adjacent semiconductor fin structure;
- a plurality of gate structures extending in a second direction transverse to the first direction, wherein each gate structure overlies a respective semiconductor fin section and is in contact with the first major sidewall and the second major sidewall of the respective semiconductor fin section;
- and
- regions of stress/strain inducing material partially filling the gaps, wherein each region of stress/strain inducing material contacts the second end sidewall of each selected semiconductor fin structure and the first end sidewall of the respective adjacent semiconductor fin structure.
A semiconductor device comprising:
- a semiconductor fin extending along a first direction and having an upper surface interrupted by gaps to form discontinuous upper surface segments, wherein each upper surface segment ends at a respective first end sidewall and a respective second end side wall, and wherein each gap is bounded in the first direction by a selected first end sidewall and an adjacent second end sidewall;
- and
- a stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall.
Dependencies are inferred from the claim text.